Programmable logic devices exist as a well-known type of integrated circuit that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices CPLDs). One type of programmable logic devices, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time to market and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
The process for producing an integrated circuit comprises many steps. Conventionally, a logic design is followed by a circuit design, which is followed by a layout design. With respect to the circuit design and layout portion, once circuits for an integrated circuit have been designed, such designs are converted to a physical representation known as a “circuit layout” or “layout.” Layout is exceptionally important to developing a working design as it affects many aspects, including, but not limited to, signal noise, signal time delay, resistance, cell area, and parasitic effect.
Once a circuit is designed and laid out, it is often simulated to ensure performance criteria are met, including, but not limited to, signal timing. This type of analysis is difficult at the outset, and is made more difficult by an embedded design. An embedded design or embedded circuit is conventionally designed separately from an integrated circuit in which it is embedded. Sometimes this embedded circuit is referred to an intellectual property (IP) core or embedded core. This is because the information to build and test such an embedded circuit is provided from one company to another.
An IP core may have a certain maximum timing performance for input and output. For example, a microprocessor will have certain maximum timing performance for input and output of data and other information. However, there is no de facto standard bus interface for an embedded device. Accordingly, glue or gasket logic and interconnects are used to couple an embedded device to a host device, such as a programmable logic device.
For an embedded core in an integrated circuit, such as an FPGA with an embedded microprocessor core, a portion of the integrated circuit is reserved for the embedded core and gasket/glue logic. In this reserved area, interconnects and gasket logic may be used to couple an embedded core to a host integrated circuit. Moreover, modules from a host integrated circuit may be used for this coupling. However, layout for an embedded device and a host device may be for different layout databases. Thus, understanding where critical time paths are becomes problematic.
Moreover, different layout databases based on different dimensions lead to manual evaluation. However, this was considerably slow and error prone. Furthermore, re-simulation and re-design was slowed by having to manually make changes.
Accordingly, it would be desirable and useful to provide means to automate gathering of gasket timing information from dissimilar layout databases for analysis, and more particularly to provide a self-contained timing model analysis capable of accommodating different layout databases with different process technologies.